Low depth carry lookahead addition using charge recycling threshold logic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Celinski, Peter ^a   Al Sarawi, Said ^a   Abbott, Derek ^a   López, José F ^a  

^a UNIVERSITY OF ADELAIDE   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BINARY SEQUENCES; BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; LOGIC GATES;

CARRY LOOKAHEAD ADDITION; CHARGE RECYCLING THRESHOLD LOGIC; THRESHOLD LOGIC GATE;

LOGIC DESIGN;

EID: 0036292168     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Low power, high speed, charge recycling CMOS threshold logic gate
2. A capacitive threshold-logic gate
3. Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment
4. Asynchronous sense differential logic
5. Compact four bit carry look-ahead CMOS adder in multi-output DCVS logic