Low-power register-exchange viterbi decoder for high-speed wireless communications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  El Dib, Dalia A F ^a   Elmasry, Mohamed I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTER SIMULATION; CONVOLUTIONAL CODES; DECODING; MICROCONTROLLERS; SHIFT REGISTERS; SIGNAL TO NOISE RATIO; VERY LONG INSTRUCTION WORD ARCHITECTURE; WIRELESS TELECOMMUNICATION SYSTEMS;

HIGH-SPEED WIRELESS COMMUNICATION; REGISTER-EXCHANGE METHOD; SURVIVOR MEMORY UNIT; TRACE-BACK METHOD; VITERBI DECODER;

ENCODING (SYMBOLS);

EID: 0036291071     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Low-power viterbi decoder for CDMA mobile terminals
2. Error bounds for convolutional codes and asymptotically optimum decoding algorithm
3. The viterbi algorithm
4. Viterbi decoder design for the IS-95 CDMA forward link
5. Lower power Viterbi decoder architecture with a new clock-gating trace-back unit
6. High-rate Viterbi processor: A systolic array solution
7. A -Mb/s 256-state 10-mW rate-1/3 Viterbi decoder
8. Low power ACS unit design for the Viterbi decoder
9. Maximum weight basis decoding of convolutional codes
10. Low latency sequential decoding
11. Power consumption estimation in CMOS VLSI chips