An adaptive data compression scheme for memory traffic minimization in processor-based systems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Benini, Luca ^a   Bruni, Davide ^a   Riccò, Bruno ^a   Maccii, Alberto ^a   Maccii, Enrico ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; CONSTRAINT THEORY; DATA COMPRESSION; DATA STORAGE EQUIPMENT;

DECOMPRESSION; MEMORY TRAFFIC MINIMIZATION;

PROGRAM PROCESSORS;

EID: 0036287686     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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7. Selective instruction compression for memory energy reduction in embedded systems
8. Hardware-assisted data compression for energy minimisation in systems with embedded processors
9. A universal algorithm for sequential data compression
10. Arithmetic coding for data compression
11. Evaluating future microprocessors - The simplescaler toolset