Automated test development and test time reduction for RF subsystems

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages 581-584

  Ozev, Sule ^a   Orailoglu, Alex ^a   Haggag, Hosam ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b National Semiconducto   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; FREQUENCY DOMAIN ANALYSIS; FREQUENCY METERS; TIME DOMAIN ANALYSIS;

AUTOMATED TEST DEVELOPMENT; RADIO FREQUENCY SUBSYSTEMS; TEST TIME REDUCTION;

DESIGN FOR TESTABILITY;

EID: 0036287303     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1009907     Document Type: Article

References (7)

1. An architecture for self-test of a wireless communication system using sampled IQ modulation and boundary scan
2. End-to-end test strategy for wireless systems
3. Analog circuit testing based on sensitivity computation and new circuit modeling
4. An integrated approach for analog circuit testing with a minimum number of detected parameters
5. Parametric fault simulation and test vector generation
6. Testability implications for low-cost integrated radio transceivers: A blue-tooth case study
7. Test selection based on high level fault simulation for mixed-signal systems