Test selection based on high level fault simulation for mixed-signal systems

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 149-154

  Ozev, Sule ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR DETECTION; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; PROBABILITY; RELIABILITY; YIELD STRESS;

BLOCK LEVEL MODELING; HIGH LEVEL FAULT SIMULATION; MIXED SIGNAL SYSTEMS;

INTEGRATED CIRCUIT TESTING;

EID: 0033733913     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (10)