A 2-stage matching scheduler for a VOQ packet switch architecture

IEEE International Conference on Communications

Volumn 4, Issue , 2002, Pages 2105-2110

  Jiang, Ying ^a   Hamdi, Mounir ^b  

^a Suntek Technology Co Ltd   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SIMULATION; ITERATIVE METHODS; QUEUEING NETWORKS; SCHEDULING; SYNCHRONIZATION; TELECOMMUNICATION TRAFFIC;

ARBITER POINTERS; VIRTUAL OUTPUT QUEUING (VOQ);

PACKET SWITCHING;

EID: 0036285366     PISSN: 05361486     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICC.2002.997219     Document Type: Article

References (12)

1. Input versus output queuing on a space-division packet switch
2. High speed switch scheduling for local area networks
3. Analysis of nonblocking ATM switches with multiple input queues
4. Achieving 100% throughput in an input- queued switch
5. A practical scheduling algorithm to achieve 100% throughput in input-queued switches
6. Centralized contention resolution schemes for a large-capacity optical ATM switch
7. FIRM: A class of distributed scheduling algorithms for high-speed ATM switches with multiple input queues
8. Data structures and network algorithms
9. 5/2 algorithm for maximum matching in bipartite graphs
10. The tiny tera: A small high-bandwidth packet switch core
11. A fully desynchronized round-robin matching scheduler for a VOQ packet switch architecture