Fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 98-103

  Um, Junhyung ^a   Kim, Taewhan ^a   Liu, C L ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; COSINE TRANSFORMS; DIGITAL ARITHMETIC; IIR FILTERS; KALMAN FILTERING; LOGIC CIRCUITS; LOGIC GATES; OPTIMIZATION;

ARITHMETIC CIRCUIT; BIT LEVEL CARRY SAVE CONDITION; LOGIC SYNTHESIS; WALLACE SCHEME;

LOGIC DESIGN;

EID: 0033682562     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)