Implementation of a third-generation 1.1 GHz 64 b microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 338-339+472+333

  Konstadinidis, Georgios ^a   Normoyle, Kevin ^a   Wong, Samson ^a   Bhutani, Sutikshan ^a   Stuimer, Harry ^a   Johnson, Timothy ^a   Smith, Alan ^a   Cheung, Daniel ^a   Romano, Fabrizio ^a   Yu, Shifeng ^a   Oh, Sung Hun ^a   Melamed, Victor ^a   Narayanan, Shridar ^a   Bunsey, David ^a   Khieu, Cong ^a   Wu, Kevin J ^a   Schmitt, Ralf ^a   Dumlao, Andy ^a   Sutera, Massimo ^a   Chau, Jade ^a   James Lin, K ^a   more..

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER WORKSTATIONS; MULTIPROCESSING SYSTEMS; PACKET SWITCHING; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; SERVERS; TRANSISTORS;

THIRD-GENERATION MICROPROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0036114652     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. A 3rd generation SPARC V9 64-b microprocessor
2. UltraSPARC-III: A 3rd-generation 64 b SPARC microprocessor
3. Implementation of a 3rd-generation SPARC V9 64 b microprocessor
4. Introducing the ultraSPARC(TM)-IIIi microprocessor
5. Two FIFO ring performance experiments