Multi-valued flip-flop with neuron-CMOS NMIN circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2002, Pages 282-288

  Inaba, Motoi ^a   Tanno, Koichi ^b   Ishizuka, Okihiko ^b  

^a TSUKUBA UNIVERSITY OF TECHNOLOGY   (Japan)

^b UNIVERSITY OF MIYAZAKI   (Japan)

Author keywords

Analog inverter; Down literal circuit; Multi valued flip flop; NMIN circuit; Voltage comparator

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; LOGIC CIRCUITS; NAND CIRCUITS; VLSI CIRCUITS;

ANALOG INVERTER; DOWN LITERAL CIRCUIT; MULTI-VALUED FLIP-FLOP; NMIN CIRCUITS;

FLIP FLOP CIRCUITS;

EID: 0036080031     PISSN: 0195623X     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISMVL.2002.1011100     Document Type: Article

References (9)

1. Functional MOS transistor featuring gate-level weighted sum and threshold operation
2. Down literal circuit with neuron-MOS transistors and its applications
3. Voltage-mode variable threshold circuits with neuron MOS transistors for multi-valued logic
4. Analog inverter with neuron-MOS transistors and its application
5. Realization of NMAX and NMIN functions with multi-valued voltage comparator
6. Multiple valued logic static latch circuits
7. Circuit design of a ternary flip-flop using ternary logic gates
8. A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors