METRO-3D: An efficient three-dimensional wafer inspection simulator for next generation lithography

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2002, Pages 396-401

  Zhu, Zhengrong ^a   Swecker, Aaron L ^a   Strojwas, Andrzej J ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTROMAGNETIC FIELDS; LIGHT POLARIZATION; OPTIMIZATION; PERMITTIVITY; PHOTOLITHOGRAPHY; SILICON WAFERS; SURFACE TOPOGRAPHY; THREE DIMENSIONAL; WAVEGUIDES;

NEXT GENERATION LITHOGRAPHY; NUMERICAL APERTURE; SOFTWARE PACKAGE METRO-3D;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036078789     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. International technology roadmap for semiconductors
2. Efficient light scattering modeling for alignment, metrology an resist exposure in photolithography
3. Efficient and rigorous three-dimensional model of optical lithography simulation
4. Comparison of defect detection schemes using rigorous 3-D EM field simulations
5. New formulation of the Fourier modal method for crossed surface-relief gratings
6. Simulation of defect detection schemes for wafer inspection in VLSI manufacturing
7. Three dimensional modeling of wafer inspection schemes for sub-70 nm lithography