Yield prediction using critical area analysis with inline defect data

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2002, Pages 82-86

  Zhou, Carl ^a   Ross, Ron ^a   Vickery, Carl ^a   Metteer, Brian ^a   Gross, Steve ^a   Verret, Doug ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Critical area; Defect; Inline inspection; Yield; Yield prediction

Indexed keywords

CRYSTAL DEFECTS; FAILURE ANALYSIS; INSPECTION; MATHEMATICAL MODELS; RANDOM PROCESSES;

CRITICAL AREA ANALYSIS; DEFECT SIZE DISTRIBUTION; LASER SCATTEROMETRY;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036075989     PISSN: 1523553X     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASMC.2002.1001579     Document Type: Article

References (9)

1. Computation of the critical area in semiconductor yield theory
2. Yield estimation model for VLSI artwork evaluation
3. Modeling of critical area in yield forecasts
4. In-line yield prediction methodologies using patterned wafer inspection information
5. Application of a survey sampling critical area computation tool in a manufacturing environment
6. Integrated circuit yield statistics
7. Yield, economic, and logistic models for complex digital arrays
8. Large-area clusters and fault tolerance in VLSI circuits: A review
9. Beta evaluation of the KLA-Tencor A1T2