A differentially-tuned CMOS LC VCO for low-voltage full-rate 10 Gb/s CDR circuit

IEEE MTT-S International Microwave Symposium Digest

Volumn 2, Issue , 2002, Pages 707-710

  Mukherjee, Debanjan ^a   Bhattacharjee, Jishnu ^a   Laskar, Joy ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; OPTICAL COMMUNICATION; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE;

CARRIER FREQUENCY; CLOCK AND DATA RECOVERY CIRCUITS; PHASE NOISE;

VARIABLE FREQUENCY OSCILLATORS;

EID: 0036069635     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Jitter in ring oscillators
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5. A 155-MHz clock recovery delay-and phase-locked loop
6. A 1.8V 3mw 16.8GHz frequency divider in 0.25μm CMOS
7. Design techniques for low-voltage high-speed digital bipolar circuits
8. A 10-Gb/s CMOS clock and recovery circuit with a half-rate linear phase-detector