Extraction of a polynomial LDMOS model for distortion simulations using small-signal S-parameter measurements

IEEE MTT-S International Microwave Symposium Digest

Volumn 3, Issue , 2002, Pages 2157-2160

  Vuolevi, Joel ^a   Aikio, Janne ^a   Rahkonen, Timo ^a  

^a UNIVERSITY OF OULU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC DISTORTION; ELECTRIC NETWORK ANALYZERS; INTEGRATED CIRCUITS; POLYNOMIALS;

POLYNOMIAL EXTRACTION TECHNIQUE; S-PARAMETER MEASUREMENTS; THIRD ORDER INTERMODULATION DISTORTION;

FIELD EFFECT TRANSISTORS;

EID: 0036063377     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Extraction of a nonlinear AC FET model using small-signal S-parameters
2. 16-term error model and calibration procedure for on-wafer network analysis measurements
3. MOS transistor modeling for RF IC design
4. Measurement technique for characterizing memory effects in RF power amplifiers
5. A Volterra model for common-source FET amplifiers in third order intermodulation distortion simulations