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Volumn , Issue , 2001, Pages 25-34

Dynamic hardware plugins (DHP): Exploiting reconfigurable hardware for high-performance programmable routers

Author keywords

active networking; port processor; Programmable router; reconfigurable hardware

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING; DYNAMIC LOADS; HARDWARE; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; ROUTERS;

EID: 84962194782     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OPNARC.2001.916836     Document Type: Conference Paper
Times cited : (19)

References (17)
  • 2
    • 84962187205 scopus 로고    scopus 로고
    • Virtex-E 1.8V Field Programmable Gate Arrays
    • February 29, San Jose, CA
    • Xilinx, Inc. "Virtex-E 1.8V Field Programmable Gate Arrays", Advance Product Specification, February 29, 2000, San Jose, CA.
    • (2000) Advance Product Specification
    • Xilinx, Inc.,1
  • 9
    • 0007966184 scopus 로고    scopus 로고
    • Designing a Multimedia Subsystem with Rambus DRAMs
    • March Miller Freeman, Inc.
    • Warmke, R., "Designing a Multimedia Subsystem with Rambus DRAMs", Multimedia Systems Design, March 1998, Miller Freeman, Inc.
    • (1998) Multimedia Systems Design
    • Warmke, R.1
  • 12
    • 0004512317 scopus 로고    scopus 로고
    • An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists
    • National Institute of Standards and Technology, Gaithersburg, MD, April
    • A. Elbirt, et al., "An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists," AES3: The Third Advanced Encryption Standard (AES) Candidate Conference, National Institute of Standards and Technology, Gaithersburg, MD, April 2000.
    • (2000) AES3: The Third Advanced Encryption Standard (AES) Candidate Conference
    • Elbirt, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.