A 1.29 um2 full CMOS ultra-low power SRAM cell with 0.12um spacer-on-stopper (SOS) CMOS technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 253-256

  Kim, Sung Bong ^a   Kim, Do Hyung ^a   Koh, Kwang Ok ^a   Park, Yong ^a   Lee, Han Shin ^a   Park, Jai Kyun ^a   Joo, Joon Yong ^a   Kim, Jin Ho ^a   Hwang, Byung Joon ^a   Kim, Moo Sung ^a   Lee, Ji Young ^a   Lee, Suk Joo ^a   Park, Seung Hyun ^a   Hong, Jung In ^a   Lee, Moon Yong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MASKS; MICROELECTRONIC PROCESSING; PHOTOLITHOGRAPHY; SEMICONDUCTOR DEVICE STRUCTURES; STATIC RANDOM ACCESS STORAGE;

BAND TO BAND TUNNELING LEAKAGE; GATE PATTERNS; OPTICAL ENHANCEMENT TECHNIQUE; PHASE SHIFT MASK; PHOTO RESIST FLOW; SPACER ON STOPPER TECHNOLOGY; ULTRA LOW POWER CELL;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035717074     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)