Coordinated transformations for high-level synthesis of high performance microprocessor blocks

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 898-903

  Gupta, Sumit ^a   Kam, Timothy ^a   Kishinevsky, Michael ^a   Rotem, Shai ^a   Savoiu, Nick ^a   Dutt, Nikil ^a   Gupta, Rajesh ^a   Nicolau, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

High level synthesis; Microprocessor design

Indexed keywords

HIGH-LEVEL SYNTHESIS (HLS);

DECODING; MICROCOMPUTERS; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS;

MICROPROCESSOR CHIPS;

EID: 0036048303     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012749     Document Type: Article

References (19)

1. Optimizing resource utilization using transformations
2. Behavioral transformation for algorithmic level IC design
3. Sehwa: A software package for synthesis of pipelines from behavioral specifications
4. Force-directed scheduling for the behavioral synthesis of ASIC’s
5. Global scheduling independent of control dependencies based on condition vectors
6. A new symbolic technique for control-dependent scheduling
7. Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions
8. A reordering technique for efficient code motion
9. Conditional speculation and its effects on performance and area for high-level synthesis
10. Trace scheduling: A technique for global microcode compaction
11. An efficient, global resource-directed approach to exploiting instruction-level parallelism
12. Synthesizing a long latency unit within VLIW processor
13. Speculation techniques for high level synthesis of control intensive designs
14. Trailblazing: A hierarchical approach to percolation scheduling