Thin-layer silicon-on-insulator high-voltage PMOS device and application

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2002, Pages 73-76

  Letavic, T ^a   Albu, R ^a   Dufort, B ^a   Petruzzello, J ^a   Simpson, M ^a   Mukherjee, S ^a   Weijland, I ^a   Van Zwol, H ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC PROPERTIES; ELECTRIC BREAKDOWN; METALLIZING; MOS DEVICES; SEMICONDUCTOR JUNCTIONS;

DIELECTRIC DEPOSITION;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0036047478     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Realization of high breakdown voltage (> 700 V) in thin SOI devices
2. High voltage ldmos transistors in sub-micron soi films
3. High performance 600 V smart power technology based on thin layer silicon-on-insulator
4. 3d resurf double-gate MOSFET
5. 600 v power conversion system-on-a-chip based on thin layer SOI
6. High-voltage, double-gate devices on silicon-on-insulator
7. Lateral smart discrete process and devices based on thin layer SOI
8. A low loss high-frequency half-bridge driver with integrated power devices using ez-hv soi technology