High performance 600 V smart power technology based on thin layer silicon-on-insulator

IEEE International Symposium on Power Semiconductor Devices & ICs (ISPSD)

Volumn , Issue , 1997, Pages 49-52

  Letavic, T ^a   Arnold, E ^a   Simpson, M ^a   Aquino, R ^a   Bhimnathwala, H ^a   Egloff, R ^a   Emmerik, A ^a   Wong, S ^a   Mukherjee, S ^a  

^a PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC RESISTANCE; MOSFET DEVICES; POWER ELECTRONICS; SEMICONDUCTOR DEVICE STRUCTURES; SUBSTRATES; THIN FILMS;

BONDED SILICON ON INSULATOR (BSOI) SUBSTRATES; LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTORS (LDMOS);

SILICON ON INSULATOR TECHNOLOGY;

EID: 0030650598     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)