A non-linearity self-calibration technique for delay-locked loop delay-lines

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn 2, Issue , 2002, Pages 1007-1010

  Baronti, F ^a   Fanucci, L ^a   Lunardini, D ^a   Roncella, R ^a   Saletti, R ^a  

^a CNR   (Italy)

Author keywords

Delay locked loop delay lines; Differential non linearity; High resolution time measurement; No linearity calibration technique; Time to digital converters

Indexed keywords

ALGORITHMS; CALIBRATION; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL CONTROL SYSTEMS; DIGITAL INTEGRATED CIRCUITS; FEEDBACK; INTEGRATED CIRCUIT LAYOUT; SCHEMATIC DIAGRAMS;

DELAY LOCKED LOOP DELAY LINES; DIFFERENTIAL NONLINEARITY; HIGH RESOLUTION TIME MEASUREMENT; NONLINEARITY SELF CALIBRATION; TIME TO DIGITAL CONVERTERS;

ELECTRIC DELAY LINES;

EID: 0036044568     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1109/IMTC.2002.1007092     Document Type: Article

References (8)

1. A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level
2. A virtual clock enhancement method for DDS using an analog delay line
3. A 900-MHz oscillator using a DLL-based frequency multiplier technique for PCS applications
4. Multihit multichannel time-to-digital converter with +-1% differential nonlinearity and near optimal time resolution
5. A high-resolution time interpolator based on a delay locked loop and an RC delay line
6. On-line calibration for non-linearity reduction of delay-locked delay-lines
7. A digitally controlled shunt capacitor CMOS delay line
8. Full speed testing of A/D converters