Quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC microprocessor

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 71-74

  Bhadra, Jayanta ^a   Abadir, Magdy S ^a   Abraham, Jacob A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS;

AUTOMATIC TEST PATTERN GENERATION; FALSE CRITICAL PATH IDENTIFICATION; STATIC TIMING ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0033712914     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)