Approaching the one billion transistor logic product: Process and design challenges

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4692, Issue , 2002, Pages 254-261

  Sery, George E ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Device control; Microprocessor; OPC; Transistor scaling

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA STRUCTURES; DATABASE SYSTEMS; DIELECTRIC DEVICES; TRANSISTORS;

CRITICAL DIMENSION CONTROL;

MICROPROCESSOR CHIPS;

EID: 0036030920     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.475662     Document Type: Conference Paper

References (7)

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3. G. Marcyk and R. Chau, 'New Transistors for 2005 and Beyond', Intel Developer's Forum, Nov 26, 2001.
4. R. Chau, 'A 50nm Depleted-Substrate CMOS Transistor (DST)', in IEEE Int. Electron Device Meeting, Dec 2001.
5. R. Chau, 'High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics', in IEEE Int. Electron Device Meeting, Dec 2001.
6. International Technology Roadmap for Semiconductors, 2001 Edition.
7. K.A. Bowman, S.G. Duvall, and J.D. Meindl, 'Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration', IEEE J. Solid-State Circuits, vol 37, pp. 183-190.