Die-scale wafer flatness: 3-dimensional imaging across 20 mm with nanometer-scale resolution

Proceedings of SPIE-The International Society for Optical Engineering

Volumn 4689 II, Issue , 2002, Pages 812-816

  Miller, Kirk ^a   Fong, David ^a   Dawson, Dean ^a   Todd, Bradley ^a  

^a Veeco Metrology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; FORMAL LOGIC; IMAGING TECHNIQUES; MEASUREMENTS; PHOTOLITHOGRAPHY;

ATOMIC FORCE PROFILERS (AFP);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036030237     PISSN: 0277786X     EISSN: None     Source Type: Journal    
DOI: 10.1117/12.473527     Document Type: Article

References (6)

1. International Technology Roadmap for Semiconductors, http://public.itrs.net.
2. H. Stauch, K. Simon, et al., "Impact of chuck flatness on wafer distortion and stepper overlay: comparison of experimental and FEM results," Microelectronic Engineering, v. 23, p. 197, 1994.
3. S. Sethi, S. Pushpala, et al., "Advanced photolithographic process modeling and characterization via wafer flatness measurements," SPIE proceedings, v. 2196, p. 283, 1994.
4. P. Govil, J. Tsacoyeanes, et al., "Contributors to focal plane nonuiformity and their impact on linewidth control in a DUV step & scan system," SPIE proceedings, v. 3334, p. 92, 1998.
5. T. Muller, R. Kumpe, et al., "Techniques for analyzing nanotopography on polished silicon wafers," Microelectronic Engineering, v. 56, p. 123, 2001.
6. Y. Zhang, L. Wagner, et al., "Importance of wafer flatness for CMP and lithography," SPIE proceedings, v. 3050, p. 266, 1997.