Techniques for analysing nanotopography on polished silicon wafers

Microelectronic Engineering

Volumn 56, Issue 1-2, 2001, Pages 123-127

  Muller T ^a   Kumpe, R ^a   Gerber, H A ^a   Schmolke, R ^a   Passek, F ^a   Wagner, P ^a  

^a SILTRONIC AG   (Germany)

Author keywords

Geometry measurements; PSD; Surface inspection; Surface roughness; Waviness

Indexed keywords

COMPUTATIONAL GEOMETRY; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; PRECISION ENGINEERING; SURFACE ROUGHNESS;

NANOTOPOGRAPHY;

SILICON WAFERS;

EID: 0035341697     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(00)00513-X     Document Type: Article

References (9)

1. National Technology Roadmap for Semiconductors (NTRS) (1999).
2. K.V. Ravi, Future Fab Int. 7 (1999) 207-212.
3. J.C. Stover, V.I. Ivakhnenko, C.A. Scherr, SPIE (1996).
4. B.W. Scheer, Micro, June (1996).
5. P. Wagner, H.A. Gerber, R. Schmolke, R. Velten, SPIE 2862 (1996) 152ff.
6. SEMATECH Technology Transfer # 95082941A-TR.
7. M.W. Mitchell, D.A. Bonnell, J. Mater. Res. 5(10) (1990).
8. ASTM 1997, F 1811-97.
9. Interferometer: SFT 4000; mech. Profiler: Dektak V300Si, both Veeco Metrology Corporation.