Fully monolithic integrated 43 Gbit/s clock and data recovery circuit in InP HEMT technology

Electronics Letters

Volumn 37, Issue 20, 2001, Pages 1235-1237

  Murata, K ^a   Sano, K ^a   Sano, E ^a   Sugitani, S ^a   Enoki, T ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; ERROR ANALYSIS; GATES (TRANSISTOR); HIGH ELECTRON MOBILITY TRANSISTORS; MATHEMATICAL MODELS; MONOLITHIC INTEGRATED CIRCUITS; OPTICAL FIBERS; PHASE LOCKED LOOPS; SEMICONDUCTING INDIUM GALLIUM ARSENIDE;

CLOCK AND DATA RECOVERY (CDR) CIRCUITS; PSEUDORANDOM BIT SEQUENCE (PRBS) SIGNAL;

OPTICAL COMMUNICATION EQUIPMENT;

EID: 0035959735     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20010837     Document Type: Article

References (9)

1. A fully-integrated 40 Gbit/s clock and data recovery/l:4 DEMUX IC in SiGe technology
2. A complete GaAs HEMT single chip data receiver for 40 Gbit/s data rates
3. Interface for optical transport network (OTN)
4. 3.5-Gb/s × 4-ch Si bipolar LSIs for optical interconnections
5. A monolithic 156 Mb/s clock and data recovery PLL circuit using the sample-and-hold technique
6. A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs
7. A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having 500-ps single shot resolution
8. 0.1μm InAlAs/InGaAs HEMT with an InP-recess-etch stopper grown by MOCVD
9. 70-Gbit/s multiplexer and 50-Gbit/s decision IC modules using InAlAs/InGaAs/InP HEMTs