Interconnect implications of growth-based structural models for VLSI circuits

2001 International Workshop on System-Level Interconnect Prediction (SLIP 2001)

Volumn , Issue , 2001, Pages 99-106

  Cheng, Chung Kuan ^a   Kahng, Andrew B ^a,b   Liu, Bao ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ESTIMATION; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS;

POWER-LAW SCALING;

VLSI CIRCUITS;

EID: 0035788912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368640.368730     Document Type: Conference Paper

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