Relaxed partitioning balance constraints in top-down placement

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1998, Pages 229-232

  Caldwell, Andrew E ^a   Kahng, Andrew B ^a   Markov, Igor L ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

TOP-DOWN PARTITIONING-BASED PLACEMENT TOOL;

ELECTRIC NETWORK SYNTHESIS;

EID: 0031639865     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)