A cooperative research for experimental characterization of signal integrity in deep submicron integrated circuits

IEEE International Symposium on Electromagnetic Compatibility

Volumn 1, Issue , 1999, Pages 361-364

  Sicard, E ^a   Delmas, S ^a   Caignet, F ^a   De Smedt, R ^b   Steinecke, T ^c   Ferrante, J G ^d   Saintot, P ^e  

^a EMC for Component   (France)

^b LUCENT TECHNOLOGIES   (United States)

^c SIEMENS AG   (Germany)

^d MATRA Systemes & Information   (France)

^e STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CROSSTALK; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SPURIOUS SIGNAL NOISE; VOLTAGE CONTROL;

CROSSTALK DELAY; DEEP SUBMICRON TECHNOLOGY; SIGNAL INTEGRITY;

ELECTROMAGNETIC COMPATIBILITY;

EID: 0033337642     PISSN: 10774076     EISSN: 21581118     Source Type: Conference Proceeding    
DOI: 10.1109/ISEMC.1999.812928     Document Type: Conference Paper

References (4)

1. The National Technology Roadmap for Semiconductors, Semiconducteur Industry Association, 1997 http://www.sematech.org/public
2. S. Criel, F. Bonjean, R. De Smedt, J. De Moerleoose, L. Martens, F. Olyslager, D. De Zutter "Accurate Characterization of Some Radiative EMC Phenomena at Chip Level", IEEE EMC Symposium, Denver, Aug 98, pp 734-738
3. nd IEEE Workshop on Signal Propagation On Interconnects, Travemunde May 1998.
4. T. Steinecke, M. Anfang "Reducing Electromagnetic emission on chip", Siemens Journal Components, No 3, 98, pp 22-25