Evaluation of embedded power technology for IPEM packaging applications

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4587, Issue , 2001, Pages 394-398

  Liang, Zhenxian ^a   Lee, Fred C ^a   Van Wyk, J D ^a   Lu, G Q ^a  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

3 D MCM; Deposited metallization interconnect; Integration packaging of power electronics modules; Screen printed dielectric isolation

Indexed keywords

DEPOSITION; METALLIZING; MICROPROCESSOR CHIPS; MOSFET DEVICES; MULTICARRIER MODULATION; POWER ELECTRONICS; SURFACE MOUNT TECHNOLOGY; THICK FILMS;

INTEGRATED POWER ELECTRONIC MODULES (IPEM);

ELECTRONICS PACKAGING;

EID: 0035768606     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. th international symposium on microelectronics, 1997.
2. R. Fisher, R. Fillion, J. Burgess, and W. Hennessy, "High frequency, low cost, power packaging using thin film power overlay technology", Proceedings of APEC'95, pp.12-17, 1995.
3. A. Collado, X. Jorda, E.Cabruja, and P. Godignon, "MCM-D packaging for power applications", Proceedings of International workshop on Integrated Power Packaging, July 14-16, Boston, P.69, 2000.
4. S. Haque, K. Xing, R-L. Lin, C. Suchicital, G-Q. Lu, D.J. Nelson, D. Borojevic, and F.C. Lee, "An innovative technique for packaging power electronics building blocks using metal posts interconnected parallel plate structures," IEEE- CPMT transaction, part B, May 1999.
5. A. Pirond, G. Nicoletto, P. Cova, M. Pasqualetti, M. Portesine, and P.E. Zani, "Thermomechanical simulation of a multichip press- packed IGBT", Solid-state Electronics, Vol.42, pp.2303-2307, 1998.
6. A.B. Lostetter, F. Barlow, and A. Elshabini, "Multilayer interconnects for a high power packaging strategy," Proceedings of IMAPS 1998 International Symposium on Microelectronics, San Diego, pp.330-334. 1998.
7. J.A.Ferreira, I.W. Hofsajer, and J.D. Van Wyk, "Exploiting the third dimension in power electronics packaging", Proceedings of APEC'97, pp.419-423, 1997.
8. Z.X. Liang, G-Q. Lu, D. Borojevic, and F.C. Lee, "Multilayer integration technology for packaging of IPEM", Proceedings of 17th CPES Seminar, Sept 1999.
9. Z.X. Liang, F.C. Lee, G-Q. Lu, and D. Borojevic, "Embedded Power - a multilayer integration technology for packaging of IPEMs and PEBBs," Proceedings of International Workshop on Integrated Power Packaging, Waltham, MA, July 14-16, P.41, 2000.
10. th VPEC Seminar, pp.107-114, 1997.