Performance optimization of the double exposure alternating PSM for (sub-) 100 nm ICs

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4562 I, Issue , 2001, Pages 394-405

  Vandenberghe, Geert ^a   Driessen, Frank ^a,b   Van Adrichem, Paul ^a,b   Ronse, K ^a   Li, Jason ^b   Karklin, Linard ^b  

^a IMEC   (Belgium)

^b SYNOPSYS INC   (United States)

Author keywords

100 nm node; ArF; CMOS; Double exposure; Phase shift; Resolution enhancement

Indexed keywords

CMOS INTEGRATED CIRCUITS; ILLUMINATING ENGINEERING; IMAGING TECHNIQUES; LITHOGRAPHY; PHASE SHIFT;

PHASE-SHIFTING MASKS (PSM);

MASKS;

EID: 0035765731     PISSN: 0277786X     EISSN: None     Source Type: Journal    
DOI: 10.1117/12.458316     Document Type: Article

References (6)

1. Y.T. Wang et al., US Patent number 5,858,580 (Jan. 12, 1999).
2. G. Vandenberghe et al., ArF Lithography options for 100nm technologies, SPIE proceedings, Vol. 4346, 2001, p179.
3. W. Maurer et al., Mask specifications for 193nm lihtography, SPIE proceedings, Vol. 2884, 1996, p.562.
4. M. Levinson, N. Viswanathan and R. Simpson, Improving resolution in photolithography with a phase-shifting mask, IEEE Transactions on Electron devices, Vol. 29, 1982, p. 1812.
5. M. Levinson, Phase-shifting mask strategies: isolated dark lines, Microlithography World, Spring 1992, p. 6.
6. G. Vandenberghe et al., (sub)-100nm gate patterning using 248nm alternating PSM, SPIE proceedings, Vol. 4409, 2001, p61.