Field emitter arrays for low voltage applications with sub 100 nm apertures and 200 nm period

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 179-182

  Pflug, David G ^a   Schattenburg, Mark ^a   Smith, Henry I ^a   Akinwande, Akintunde I ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY ELEMENT METHOD; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC PROPERTIES; FINITE ELEMENT METHOD; MICROELECTROMECHANICAL DEVICES; MOSFET DEVICES; NORMAL DISTRIBUTION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; TRANSMISSION ELECTRON MICROSCOPY;

FIELD EMITTER ARRAYS; GATE APERTURE; MICROELECTRONIC DEVICES;

SEMICONDUCTOR DEVICES;

EID: 0035716616     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Physical properties of thin field cathodes, with molybdenum cones
2. Arrays of gated field-emitter cones having 0.32 mm tip-to-tip spacing
3. Field emitter array mask patterning using laser interference lithography
4. Use of interference lithography to pattern arrays of submicron resist structures for field emission flat panel displays
5. Optically matched tri-level resist process for nanostructure fabrication
6. Observation of valence band electron emission from n-type silicon field emitter arrays
7. Highly uniform and low turn-on voltage Si field emitter arrays fabricated using chemical mechanical polishing