Design and performance evaluation of Pentium® III microprocessor packaging

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2001, Pages 291-294

  Sarangi, Ananda ^a   Ji, Gang ^a   Arabi, Tawfik ^a   Taylor, Gregory F ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP CHIP DEVICES; INDUCTANCE; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES;

CONTROLLED COLLAPSE CHIP CONNECTION; FLIP CHIP PIN GRID ARRAY; INDUCTANCE REDUCTION SCHEME; MICROPROCESSOR PACKAGING; SILICON PACKAGE TECHNOLOGY;

ELECTRONICS PACKAGING;

EID: 0035704356     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plane-model
2. Power distribution system design methodology and capacitor selection for modern CMOS technology