Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plané model

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 3, 2000, Pages 361-367

  Li, Yuan Liang ^a   Yew, Teong Guang ^b   Chung, Chee Yee ^a   Figueroa, David G ^a  

^a INTEL CORPORATION   (United States)

^b Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

Capacitor; Integrated capacitor via plane model; Power deliver

Indexed keywords

CAPACITORS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; THREE DIMENSIONAL;

INTEGRATED CAPACITOR VIA PLANE MODEL; INTEGRATED MODELING METHOD; PLASTIC PIN GRID ARRAY; POWER DELIVERY;

ELECTRONICS PACKAGING;

EID: 0034239060     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.861548     Document Type: Article

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