A practical logic BIST for ASIC designs

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 457-

  Sato, Y ^a   Sato, M ^a   Tsutsumida, K ^a   Ikeya, T ^a   Kawashima, M ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; LOGIC GATES;

AUTOMATIC TEST EQUIPMENT; EMBEDDED GATE ARRAY; SCAN BASED TESTING;

BUILT-IN SELF TEST;

EID: 0035701323     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Low overhead test point insertion for scan-based BIST
2. A BIST approach for very deep sub-micron (VDSM) defects
3. An approach to improve the resolution of defect-based diagnosis
4. Test generation for multiple-threshold gate delay fault model