Wafer level and flip chip design through solder prediction models and validation

IEEE Transactions on Components and Packaging Technologies

Volumn 24, Issue 4, 2001, Pages 650-654

  Li, Li ^a,b   Yeung, Betty H ^b  

^a IEEE   (United States)

^b MOTOROLA INC   (United States)

Author keywords

Bump characterization; Fine pitch stencil print; Flip chip interconnect; Solder bump geometry prediction; Solder joint profile; Solder wafer bumping

Indexed keywords

FLIP CHIP PACKAGES;

CHIP SCALE PACKAGES; COMPUTER SIMULATION; OPTIMIZATION; PROBABILITY; SOLDERED JOINTS; SUBSTRATES; WSI CIRCUITS;

FLIP CHIP DEVICES;

EID: 0035694180     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/6144.974956     Document Type: Article

References (7)

1. Prospects of solder paste application in ultra fine pitch era
2. Plastic ball grid array solder joint considerations
3. Predictive design of flip-chip PBGA for high reliability and low cost
4. Thermal and power cycling limits of plastic ball grid array assemblies
5. Stencil printing process development for low cost flip chip interconnect
6. Solder bump size and shape modeling and experiment validation