Diagnosis of scan chain failures

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 217-222

  Wu, Yuejian ^a  

^a NORTEL NETWORKS   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHAINS; DEFECTS; DESIGN FOR TESTABILITY; FAULT DETECTION; FAULT TOLERANCE; VLSI CIRCUITS;

FAULT TYPES; HOLD TIME; SCAN CHAIN; SCAN DESIGNS; STUCK-AT FAULTS; TEST SEQUENCE; TIMING FAULT;

INTEGRATED CIRCUIT TESTING;

EID: 0000480557     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732169     Document Type: Conference Paper

References (4)

1. Kundu, S., "On Diagnosis of Faults in a Scan Chain, " Proc. VTS93., pp. 303-308.
2. Schafer, J.L., et al., "Partner SRLs for Improved Shift Register Diagnostics, " Proc. VTS92, pp. 198-201.
3. Edirisooriya, S., et al., "Diagnosis of Scan Path Failures, " Proc. VTS95, pp. 250-255.
4. Narayanan, S., et al., "An Efficient Scheme to Diagnose Scan Chains, " Proc. ITC97.