Tutorial: synchronous dynamic memory test construction a field approach

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2000, Pages 59-64

  Vollrath, Joerg ^a  

^a White Oak Semiconductor ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC POTENTIAL; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; TIMING CIRCUITS;

DATA SHEET SPECIFICATION; DYNAMIC MEMORY DEVICE; SYNCHRONOUS DYNAMIC MEMORY TEST; TEST SEQUENCE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033698651     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)