A regularity-based hierarchical symbolic analysis method for large-scale analog networks

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 11, 2001, Pages 1054-1068

  Doboli, Alex ^a,b   Vemuri, Ranga ^a,c  

^a IEEE   (United States)

^b Stony Brook University   (United States)

^c University of Cincinnati   (United States)

Author keywords

Analog synthesis and optimization; Partitioning; Structural regularity extraction; Symbolic analysis; Tabu search

Indexed keywords

LARGE SCALE ANALOG NETWORKS; STRUCTURAL REGULARITY; SYMBOLIC ANALYSIS METHOD; SYMBOLIC PARAMETER REGULARITY; TABU SEARCH;

ACTIVE NETWORKS; ALGORITHMS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; MATHEMATICAL MODELS; POLYNOMIALS; THEOREM PROVING;

ELECTRIC NETWORK ANALYSIS;

EID: 0035521115     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.982361     Document Type: Article

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