Integrated high-level synthesis and power-net routing for digital design under switching noise constraints

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 629-634

  Doboli, Alex ^a   Vemuri, Ranga ^b  

^a STONY BROOK UNIVERSITY   (United States)

^b University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CHIP SCALE PACKAGES; COMPUTER SIMULATION; CONSTRAINT THEORY; DIGITAL CIRCUITS; SCHEDULING; SPURIOUS SIGNAL NOISE; SWITCHING;

HIGH-LEVEL SYNTHESIS (HLS); SWITCHING NOISE CONSTRAINTS;

COMPUTER AIDED DESIGN;

EID: 0034848283     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2001.156215     Document Type: Article

References (13)

1. Behavioral network graph unifying the domains of high-level and logical synthesis
2. High-performance routing trees with identified critical skins
3. Modeling digital substrate noise injection in mixed-signal IC's
4. Unifying behavioral synthesis and physical design
5. A simple approach to modeling cross-talk in integrated circuits
6. SALSA: A new approach to scheduling with timing constraints
7. Force directed scheduling for the behavior synthesis of ASICs
8. Cone-based clustering heuristic for list-scheduling algorithms