Mechanisms of positive gate bias stress induced instabilities in power VDMOSFETs

Microelectronics Reliability

Volumn 41, Issue 9-10, 2001, Pages 1373-1378

  Stojadinovic, N ^a   Manic, I ^a   Djoric Veljkovic, S ^a   Davidovic, V ^a   Golubovic, S ^a   Dimitrijev, S ^b  

^a UNIVERSITY OF NI   (Serbia)

^b GRIFFITH UNIVERSITY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CHARGE; ELECTRIC POTENTIAL; ELECTRON TRAPS; ELECTRON TUNNELING; GATES (TRANSISTOR); SILICON;

INTERFACE TRAP DENSITIES;

MOSFET DEVICES;

EID: 0035456703     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(01)00143-3     Document Type: Article

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