Quantization noise improvement in a hybrid distributed-neuron ANN architecture

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 9, 2001, Pages 842-846

  Djahanshahi, Hormoz ^a   Ahmadi, Majid ^b   Jullien, Graham A ^c   Miller, William C ^b  

^a PMC Sierra Ltd Burnaby   (Canada)

^b UNIVERSITY OF WINDSOR   (Canada)

^c UNIVERSITY OF CALGARY   (Canada)

Author keywords

Artificial neural network (ANN); Hybrid analog digital; Quantization noise; Sigmoidal neuron; VLSI

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; ELECTRIC CURRENTS; MATHEMATICAL MODELS; MOSFET DEVICES; RANDOM PROCESSES; SIGNAL TO NOISE RATIO; SPURIOUS SIGNAL NOISE; TRANSCONDUCTANCE; VLSI CIRCUITS;

HYBRID DIGITAL-ANALOG; QUANTIZATION NOISE; SIGMOIDAL NEURON;

FEEDFORWARD NEURAL NETWORKS;

EID: 0035456445     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.964997     Document Type: Article

References (8)

1. Analysis of the effects of quantization in multilayer neural networks using a statistical model
2. The selection of weight accuracies for Madalines
3. A reconfigurable VLSI neural network
4. A unified synapse-neuron building block for hybrid VLSI neural networks
5. Digital-analog hybrid synapse chips for electronic neural networks
6. Large automatic learning, rule extraction and generalization
7. Reducing the effect of quantization by weight scaling
8. A self-scaling neural hardware structure that reduces the effect of some implementation errors