Self-scaling neural hardware structure that reduces the effect of some implementation errors

Neural Networks for Signal Processing - Proceedings of the IEEE Workshop

Volumn , Issue , 1997, Pages 588-597

  Djahanshahi, H ^a   Ahmadi, M ^a   Jullien, G A ^a   Miller, W C ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; ERROR ANALYSIS; RANDOM PROCESSES; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

SELF SCALING NEURAL HARDWARE STRUCTURE;

NEURAL NETWORKS;

EID: 0031361413     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)