Unified synapse-neuron building block for hybrid VLSI neural networks

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1996, Pages 483-486

  Djahanshahi, H ^a   Ahmadi, M ^a   Jullien, G A ^a   Miller, W C ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; CURRENT VOLTAGE CHARACTERISTICS; DIGITAL TO ANALOG CONVERSION; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; MOS DEVICES; OPTIMIZATION; VLSI CIRCUITS;

BINARY WEIGHTED CURRENT MIRRORS; NONLINEAR RESISTIVE LOAD;

NEURAL NETWORKS;

EID: 0029717018     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)