A memory/adder model based on single C60 molecular transistors

Nanotechnology

Volumn 12, Issue 3, 2001, Pages 350-357

  Stadler, R ^a   Ami, S ^b   Forshaw, M ^a   Joachim, C ^b  

^a UNIVERSITY COLLEGE LONDON   (United Kingdom)

^b CEMES CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ELECTROMECHANICAL DEVICES; EQUIVALENT CIRCUITS; FULLERENES; LOGIC DESIGN; LOGIC GATES; MOLECULES;

ELECTROMECHANICAL GRID; HYBRID-MOLECULAR ELECTRONICS; MEMORY-ADDER MODEL; SOFTWARE PACKAGE SPICE;

TRANSISTORS;

EID: 0035443553     PISSN: 09574484     EISSN: None     Source Type: Journal    
DOI: 10.1088/0957-4484/12/3/324     Document Type: Conference Paper

References (16)