Feasibility of an isolation by local oxidation of silicon without field implant

Solid-State Electronics

Volumn 45, Issue 8, 2001, Pages 1257-1263

  Fay, J L ^a,b,c   Beluch, J ^a   Despax, B ^b   Sarrabayrouse, G ^c  

^a MOTOROLA INC   (United States)

^b Laboratoire Plasma et Conversion d'Energie   (France)

^c LAAS CNRS   (France)

Author keywords

Field implant; Field inversion; Local oxidation of silicon; Nitride; PECVD oxide; Silicon

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; LEAKAGE CURRENTS; NITRIDES; OXIDATION; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION;

INTERLAYER DIELECTRICS;

SILICON;

EID: 0035416996     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(00)00260-4     Document Type: Article

References (12)

1. A review of isolation technologies - Part 4
2. Process integration of an interlevel dielectric (ILD0) module using a building-in reliability approach
3. Field inversion in CMOS double metal circuits due to carbon based SOGS
4. Field inversion generated in the CMOS double metal process due to PTEOS and SOG interactions
5. Electrical characterization of doped and undoped PECVD oxides
6. Borophosphosilicate glasses for integrated circuits
7. Comprehensive analysis of a LOCOS isolation without field implant
8. Two dimensional simulation of total dose effects on NMOSFET with lateral parasitic transistor
9. Charge pumping analysis of radiation effects in LOCOS parasitic transistors
10. Interface traps and Pb centers in oxidized (100)silicon wafers
11. Effect of device processing conditions on extended dislocations and defects in Ti-salicided source/drain regions of silicon integrated circuits
12. Positive charge increase in plasma deposited oxides induced by low pressure chemical vapor deposition of silicon nitride