On the effective deployment of functional formal verification

Formal Methods in System Design

Volumn 19, Issue 1, 2001, Pages 35-44

  Abarbanel Vinov, Yael ^a   Aizenbud Reshef, Neta ^a   Beer, Ilan ^a   Eisner, Cindy ^a   Geist, Daniel ^a   Heyman, Tamir ^a   Reuveni, Iris ^a   Rippel, Eran ^a   Shitsevalov, Irit ^a   Wolfsthal, Yaron ^a   Yatzkar Haham, Tali ^a  

^a IBM HAIFA RESEARCH LAB   (Israel)

Author keywords

Formal verification; Hardware verification; Model checking

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION LANGUAGES; CONSTRAINT THEORY; FORMAL LANGUAGES; KNOWLEDGE BASED SYSTEMS;

ARCHITECTURAL VERIFICATION; BLOCK LEVEL VERIFICATION; FORMAL VERIFICATION; HARDWARE VERIFICATION; MODEL CHECKING; SOFTWARE PACKAGE RULEBASE;

FORMAL LOGIC;

EID: 0035394098     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1011219209077     Document Type: Article

References (16)

1. An overview and application of model reduction techniques in formal verification
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4. On-the-fly model checking of RCTL formulas
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6. A methodology for formal design of hardware control with application to cache coherence protocols
7. Efficient model checking by automated ordering of transition relation partitions
8. Northstar SCU formal verification
9. High-density reachability analysis
10. Verification of electronic systems
11. Validation with guided search of the state space