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Volumn , Issue , 1998, Pages 165-171
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Overview and application of model reduction techniques in formal verification
a a
a
IBM
(United States)
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Author keywords
[No Author keywords available]
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Indexed keywords
FORMAL LOGIC;
MATHEMATICAL MODELS;
STATE SPACE METHODS;
MODEL CHECKING;
SEQUENTIAL LOGIC;
DIGITAL COMMUNICATION SYSTEMS;
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EID: 0031676041
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (4)
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References (10)
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