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Volumn , Issue , 2000, Pages 724-729
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Methodology for formal design of hardware control with application to cache coherence protocols
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
BUFFER STORAGE;
COMPUTER HARDWARE DESCRIPTION LANGUAGES;
COMPUTER SIMULATION;
FORMAL LANGUAGES;
JAVA PROGRAMMING LANGUAGE;
CACHE COHERENCE PROTOCOL;
FORMAL DESIGN;
HARDWARE CONTROL;
COMPUTER HARDWARE;
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EID: 0033698178
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (9)
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References (13)
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