Optimum voltage swing on on-chip and off-chip interconnects

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 85-88

  Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; OFF-CHIP INTERCONNECTS; ON CHIPS; OPTIMUM VOLTAGES; VOLTAGE SWINGS;

CMOS INTEGRATED CIRCUITS;

EID: 84893816814     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. D. Liu and C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips", IEEE J. of Solid-State Circuits, vol. 29, pp. 663-670, June 1994.
2. E. Berglind, L Thylen, B Jaskorzynska and C Svensson, "A Comparison of Dissipated Power and Signal-to-Noise Ratios in Electrical and Optical Interconnects", J. of Lightwave Technology, vol. 17, pp.68-73, January 1999.
3. S. Yang, et. al., "A High Performance 180nm Generation Logic Technology", 1998 Int. Electron Device Conf., Digest of Technical Papers, pp. 197-200, 1998.
4. Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi and M. Aoki, "Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's", IEEE J. of Solid-State Circuits, vol. 28, pp. 414-419, April 1993.
5. M. Hedberg and T. Haulin, "I/O Family with 200mV to 500mV Supply Voltage", 1997 IEEE International Solid State Circuit Conference, Digest of Technical Papers, pp. 340-341.
6. C. Svensson and D. Liu, "Low Power Circuit Techniques", in Low Power Design Methodologies, J. M. Rabaey and M. Pedram, eds., Kluwer Academic Publishers, 1996.
7. J. M. Rabaey, Digital Integrated Circuits, Prentice Hall, 1996, p. 474.