A 25 kV ESD proof LDMOSFET with a turn-on discharge MOSFET

IEICE Transactions on Electronics

Volumn E84-C, Issue 6, 2001, Pages 823-831

  Kawamoto, Kazunori ^a   Kohno, Kenji ^a   Higuchi, Yasushi ^a   Fujino, Seiji ^a   Shirakawa, Isao ^b  

^a DENSO CORPORATION   (Japan)

^b OSAKA UNIVERSITY   (Japan)

Author keywords

ESD; LDMOSFET; Static discharge; Thick SOI

Indexed keywords

BIPOLAR TRANSISTORS; CAPACITORS; COMPUTER SIMULATION; COUPLED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTROSTATICS; HUMAN FORM MODELS; THYRISTORS;

ELECTROSTATIC DISCHARGES; PROTECTIVE CIRCUITS;

MOSFET DEVICES;

EID: 0035367592     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (8)

1. An improvement of n-channel SOI LDMOS transistors
2. Safe operating area considerations in LDMOS transistors
3. 20 V LDMOS optimized for high drain current condition which is better, n-epi or p-epi?
4. Analysis of high current breakdown and UIS behavior of RESURF LDMOS (RLDMOS) devices
5. A new adaptive resurf concept for 20 V LDMOS without breakdown voltage degradation at high current
6. Dynamic gate coupling of NMOS for efficient ESD protection
7. Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices
8. Dynamics of power MOSFET switching under unclamped inductive loadind conditions