Computational parameter study of chip scale package array cooling

IEEE Transactions on Components and Packaging Technologies

Volumn 24, Issue 2, 2001, Pages 184-190

  Watson, Scan P ^a   Murray, Bruce T ^b   Sammakia, Bahgat G ^b  

^a Corning Inc ^*  (United States)

^b State University of New York at Binghamton   (United States)

Author keywords

Chip scale package; Electronic packaging; FLOTHERM; Thermal management

Indexed keywords

CHIP SCALE PACKAGES; COMPUTATIONAL FLUID DYNAMICS; HEAT LOSSES; HEAT RESISTANCE; PARAMETER ESTIMATION; PRINTED CIRCUIT BOARDS; THERMAL CONDUCTIVITY;

THERMAL MANAGEMENT;

COOLING SYSTEMS;

EID: 0035364508     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/6144.926381     Document Type: Article

References (12)

1. Chip-size package technology for semiconductors
2. Heat transfer and pressure drop characteristics of arrays of rectangular modules encountered in electronic equipment
3. Effects of variations in streamwise spacing and length on convection with an air cooled array
4. Cooling electronic components: Forced convection experiments with an air cooled array
5. Three-dimensional heat transfer analysis of arrays of heated square blocks
6. Numerical modeling of forced convection heat transfer for modules mounted on circuit boards
7. A comparison of computational and experimental results for flow and heat transfer from an array of heated blocks
8. FLOTHERM training course
9. Numerical study of the thermal performance of a tape ball grid array (TBGA) package
10. The validity of the boussinesq approximation for liquids and gases
11. Applying heat transfer coefficient data to electronics cooling